1. Field of the Invention
The present invention relates to an amplifier circuit, a semiconductor device, and a controlling method, and particularly to an amplifier circuit, a semiconductor device, and a controlling method that eliminate a DC (Direct Current) offset caused by variations in device characteristics of a PMOS (P-channel Metal Oxide Semiconductor) transistor and an NMOS (N-channel Metal Oxide Semiconductor) transistor forming a CMOS (Complementary Metal Oxide Semiconductor), which variations occur in each manufacturing process, and which can control gain.
2. Description of the Related Art
Recently, as the manufacturing of digital devices has increased with the progress of digital signal processing technology, a CMOS integrated circuit has been widely used in a semiconductor device provided within a digital device.
However, a high-frequency signal, a video signal, an audio signal and the like may be more easily processed as an analog signal. In addition, analog signal processing is necessary to implement an A/D (Analog/Digital) converter circuit, a D/A (Digital/Analog) converter circuit, a clock transmitting circuit, and the like.
An amplifier circuit using a CMOS inverter circuit is suitable as a circuit for the above-mentioned analog signal processing because the amplifier circuit offers high gain performance with a simple configuration. On the other hand, to use an output DC bias in an optimum state may require that operating parameters such as threshold voltage, saturation current and the like of a PMOS transistor and an NMOS transistor forming a CMOS inverter circuit perfectly coincide with each other. However, it may be impossible to make the operating parameters of the PMOS transistor and the NMOS transistor perfectly coincide with each other for manufacturing reasons, so that a circuit device may be required.
Accordingly, the present applicant has previously proposed an amplifier circuit that can control gain in a CMOS inverter circuit by setting output bias potential to an optimum value and varying bias current (for example, see Japanese Patent Laid-open No. 2003-163550, hereinafter referred to as Patent Document 1).
In the Patent Document 1, as shown in FIG. 1, an amplifier circuit 1 includes two CMOS inverter circuits, that is, a CMOS inverter circuit (hereinafter referred to as a first CMOS inverter circuit) including a PMOS transistor Qp1, a PMOS transistor Qp2, an NMOS transistor Qn1, and an NMOS transistor Qn2, and a CMOS inverter circuit (hereinafter referred to as a second CMOS inverter circuit) as a circuit for reference formed in the same manner as the first CMOS inverter circuit, the second CMOS inverter circuit including a PMOS transistor Qp3, a PMOS transistor Qp4, an NMOS transistor Qn3, and an NMOS transistor Qn4.
The amplifier circuit 1 of FIG. 1 outputs a signal voltage Vin input from a signal source 13 to an input terminal 11 as an output voltage Vout from an output terminal 12. That is, in FIG. 1, the input terminal 11 is connected to the signal source 13 and a part connecting the gate of the PMOS transistor Qp1 and the gate of the NMOS transistor Qn1 to each other. The output terminal 12 is connected to a part connecting the drain of the PMOS transistor Qp1 and the drain of the NMOS transistor Qn1 to each other.
A bias voltage source Ea is a voltage source for applying a bias voltage Vg. The bias voltage source Ea has one terminal thereof connected to the signal source 13, and has another terminal thereof connected to a ground GND (that is, grounded). A voltage source Eb is set virtually so as to apply a bias voltage occurring on an output side in performing analysis of an alternating-current signal. The voltage source Eb has one terminal thereof connected to a load resistance R0, and has another terminal thereof connected to the ground GND.
An operational amplifier 14 has a non-inverting input terminal (+) connected to a part connecting the drain of the PMOS transistor Qp3 and the drain of the NMOS transistor Qn3 to each other, an inverting input terminal (−) thereof connected to a part connecting the gate of the PMOS transistor Qp3 and the gate of the NMOS transistor Qn3 to each other, and an output terminal thereof connected to the gate of the NMOS transistor Qn2 and the gate of the NMOS transistor Qn4. Incidentally, an NMOS transistor Qn5 is provided to prevent a latch-up phenomenon occurring at a time of power startup.
In the amplifier circuit 1 of FIG. 1, a power supply voltage is represented as Vdd; a bias voltage applied by a bias voltage source Ec is represented as Vg; a voltage applied by a variable voltage source Ed is represented as Vc; a source potential of the PMOS transistor Qp1 and the PMOS transistor Qp2 and a source potential of the PMOS transistor Qp3 and the PMOS transistor Qp4 are represented as Vsp; and an output voltage of the operational amplifier 14 is represented as Vn.
That is, in the amplifier circuit 1 of FIG. 1, the same control voltage Vc (the voltage from the variable voltage source Ed) is applied to the gates of the PMOS transistor Qp2 and the PMOS transistor Qp4. The same voltage Vn for adjustment (the output voltage from the operational amplifier 14) is applied to the gates of the NMOS transistor Qn2 and the NMOS transistor Qn4.
Thus, the amplifier circuit 1 of FIG. 1 can control operating current flowing through the PMOS transistor Qp1 and the NMOS transistor Qn1 forming a CMOS inverter by the control voltage Vc supplied to the gate of the PMOS transistor Qp2.
In addition, because the operating parameters such as threshold voltage, saturation current and the like of the PMOS transistor Qp1 and the NMOS transistor Qn1 do not coincide with each other for reasons of variations in manufacturing and the like, an DC offset as an error of an output DC bias of the second CMOS inverter circuit having the same form as the first CMOS inverter circuit from an optimum bias state (for example an intermediate voltage between a GND voltage and a Vdd voltage) is detected, and the gate voltage (the voltage Vn for adjustment) of the NMOS transistor Qn4 is set so as to minimize the DC offset.
The gate voltage set in the NMOS transistor Qn4 forming the second inverter circuit is supplied as gate voltage to the NMOS transistor Qn2 forming the first CMOS inverter circuit, whereby an output DC bias of the first CMOS inverter circuit is set in an optimum bias state.
As described above, the amplifier circuit 1 of FIG. 1 can control gain by setting the output bias potential to an optimum value and making the operating current variable.